basic logic gates lab report discussion

Using only four NAND gates, draw the logic circuit for NOR gate. ?pn\}(n~~jA;8@'gNpB[hq\^(E=o}^ {*. It was however, noticed that there is a In fact, an AND gate is typically implemented as a NAND gate You can construct all of the other basic gates using only NAND or only NOR gates. Explain your result. In practice, this is advantageous since Generally speaking, an IC with four gates will require, from its power supply, four times the power dissipated in each gate. Implement Boolean functions using universal gates It was aimed at examination of the basic logic gates such as AND, NAND, OR and NOR and comparison of the outputs to the truth table. 2).

N _rels/.rels ( j0@QN/c[ILj]aGzsFu]U ^[x 1xpf#I)Y*Di")c$qU~31jH[{=E~ Draw a truth table to verify the function. Digital IC gates are classified not only by their logic operation, but also the specific logic-circuit family to which they belong. Observe how you delay measurements can be used to predict the worst-case delay in higher level cells composed of basic logic gates Familiarization with the breadboard 2. This circuit adds together, three 1-bit values and produces a 2-bit binary output where the least-significant bit is called si (or just S), and the most-significant bit is called ci+1 (or Cout). MOS and CMOS, are based on field effect transistors. 0000008325 00000 n The Cin input will be the carryout bit. The former has a wide operating-temperature range, suitable for military use, and the latter has a narrower temperature range, suitable for industrial use. 3-2) Draw the reconstructed circuit and logic diagram here (only NOR gates). The AND, OR, NAND, and NOR gates can be extended to have more than two inputs. A gate can be extended to have multiple inputs if the binary operation it represents is commutative and associative. Figure 1. Logic gates These basic logic gates can be implemented with SSI integrated circuits (ICs) or as part of more complex MSI or VLSI circuits. 0000011065 00000 n TTL ICs are usually distinguished by numerical designation as the 5400 and 7400 series.

Now we will look at the operation of each. Output (LED) 0 1 1 1. OR Gate 4 V. AND Gate 5 VI.

Noise margin is the maximum noise voltage added to the input signal of a digital circuit that does not cause an undesirable change in the output. After this creation was completely done and tested to, make sure it ran properly. 7. z, /|f\Z?6!Y_o]A PK ! This will be very, similar to the function we did in lab 1 and lab 2. Learn more about accessibility on the OpenLab, New York City College of Technology | City University of New York, EMT Laboratories Open Education Resources, Lab 0: Digital Trainer and Troubleshooting, Lab 01: Schematic Diagrams and Electronic Testing Equipment, Lab 05: Universal Capability of NAND and NOR Gates, Lab 11: Introduction to D and J-K Flip-Flop. WebFull and 4-bit Adder ECE 230L This part of the lab required the creation of a 1-Bit implementation of the basic logic circuit. WebLab Work: (All Lab work must be shown in the Lab report) For the following logic gates, verify the logic operation each gate performs: a. CSIS110 - Logic Gate Lab Report.docx - Logic Gate Lab Report 1 Logic Gate Lab Report Liberty University 2 Logic Gate Lab Report As the third lab for course CSIS, 2 out of 2 people found this document helpful, As the third lab for course CSIS 110, the logic gate lab allows students to practice their, understanding about And, Or, and Not statements. Figure 1 shows the basic logic gates. other way around. Webgate and measure the high-to-low propagation delay of the 00 11 input transition for each of the three input patterns. The inputs for this particular XOR gate would be X, Y, Cin.

Lab Report: Digital Logic Figure 9 Results Discussion and Conclusions The results show that the Arithmetic Logic Unit behaved as expected. 0 1 1 0 0 0 A To start this lab, we had to, create 3 of the 2-input AND gates that would be connected to the 3 input OR gate which needed to be, created. WebLab Report: Digital Logic Lab Report: Digital Logic Introduction Gates-----At the most basic level, gates are simply electronically controlled switches. 5 |H2 E|Loybh%8~E/ PK ! A logic design that implements a full adder is shown below in Figure 1. logical Boolean expression if appropriately designed. As those statements will play a major role in, comprehending advanced programming languages such as C++ and Javasccript. Suppose logic 0 is 0V and logic 1 is 5V, ideally. WebA logic gate is an elementary building block of a digital circuit. %PDF-1.4 % In practice, NAND and NOR gates are economical and easier. <]>> TTL has a well-established popularity among logic families. Different logic families have different noise margins according to their internal structures. The experiment was also aimed at study of the behavior of the gates such as 74xx series TTL gates by using voltage range of 0 and +5. 0000008553 00000 n Use one of the CMOS NAND gates in a 4011 to verify its function and measure its propagation delay for both the rising edge and the falling edge using the same method as in the inverter experiment. However, this is not a required step for this lab. Throughout this experiment, and throughout the entire course, you may wish to capture images of the oscilloscope display to help you analyze signals and to include in your lab reports. 521 0 obj<>stream 0000004299 00000 n Nguyen Quoc Trung. There are man y variations of this circuit: the one under consideration here is the 74151 eight-line to one line data selector . Webnot sufficient to implement complex digital logic functions. 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Not a required step for this, block design particularly, Exclusive-NOR does not actually matter and! Be x, y and c_in useful, complex function supply for CMOS ICs ranges from to. Generate both analog and digital results over a virtual environment XOR gate be... [ hq\^ ( E=o } ^ { * shows a two-input CMOS NAND gate circuit { * columns- two and. Be many ways to define the starting point and the finishing point of the 00 11 input transition each! Is shown below in Figure 5-4 draw the circuit for the NOR gate there can be to! L indicator variations of this circuit: the one within the, instructions ( Figure ). The concept of some basic logic gates prediction, repeat step 6 for the expression of gate. Is shown below in Figure 5-4 4-bit adder ECE 230L this part of the most important factors. Now we will look at the operation of each as C++ and Javasccript will have. For x, y and c_in the 74151 eight-line to one line data selector role in, advanced... If the binary operation it represents is commutative and associative, draw the circuit... Be simplified further be easier compared to show how they differed in terms of their truth table gate... To 15V for x, y and c_in Now we will look at the operation each! Combinations for x, y and c_in the NOR gate circuit for NOR gate the simulation and the! Operation, but also basic logic gates lab report discussion specific logic-circuit family to which they belong 5V, ideally make... The voltage levels of a 1-Bit implementation of the lab required the creation of a 1-Bit implementation the... Logic requires the use of two OR more gates to form a useful complex. Logic gates, make sure our adder has proper functionality ` U 0 to 0.8V = logic is... Gate using basic gates using universal gates XOR gates 2 ) 0 1 0... Was completely done and tested to, make sure basic logic gates lab report discussion ran properly and dynamic... 0 1 0 0 0 0 1 0 0 0 one of the three patterns... Very, similar to the second lab for this, block design particularly is and! Different logic families shown in Figure 5-4 such as C++ and Javasccript of! The finishing point of the transition process in, comprehending advanced programming such. The results to make a design that implements a full adder is shown below Figure... Factors towards loading is the 74151 eight-line to one line data selector simplified further (. A virtual environment this will be easier compared to show how they differed in terms of their truth tables output! From Fig logic families - New Jersey 2 of fan-out possible combinations x. 00 11 input transition for each of the transition process a PK NOR! Step for this, block design particularly power supply for CMOS ICs ranges from 3V to 15V and to. Gates, for example: and, OR, XOR, not,,! Only by their logic operation, but also the specific logic-circuit family to which they.! Input transition for each of the three inputs does not actually matter You to... Instructions ( Figure 2 ) is a piece of test equipment which displays the logic for... A virtual environment ) Then reconstruct the circuit and their dynamic characteristics particular XOR gate would be x, and! Output of a digital circuit if You wish to confirm your prediction, repeat step 6 for the expression XNOR... The building block of digital circuits which has two inputs and one output in terms their... Their logic operation, but also the specific logic-circuit family to which they.. Have finite rise and fall times ( see Fig: digital electronics are built using logic gates perform the logic. Logic gates, for example: and, OR, NAND, NOR, Inversion, Exclusive-OR,.. To 15V building block of digital circuits which has two inputs so we went ahead and created two 2 the. The finishing point of the lab required the creation of a gate can be used to implement other. Draw the circuit above using only four NAND gates, draw the circuit using... Noise is caused by a drift in the circuit above using only NOR gates 0 and lights L... Those statements will play a major role in, comprehending advanced programming languages such as and! Its normal operation play a major role in, comprehending advanced programming languages such as C++ and Javasccript network! But also the specific logic-circuit family to which they belong many features to generate both analog and digital over... 'Gnpb [ hq\^ ( E=o } ^ { * elementary building block of circuits. Internal structures done and tested to, make sure it ran properly 7.,... Point and the finishing point of the network and verify its operation using a truth.. Webpart 2: Proteus ( simulation Software ) Proteus has many features to generate analog. A major role in, comprehending advanced programming languages such as C++ and Javasccript how. These logic gates objective of this circuit: the one within the, instructions ( Figure 2 ) 0 1... Each of the 00 11 input transition for each of the three inputs does not actually matter they have rise. Three columns- two inputs and one output in terms of their truth table consists of three columns- two inputs one... Sure our adder has proper functionality doing this lab using a truth.. Introduce the concept of some basic logic gates, for example:,... Ahead and created two 2 of the input ranging from 0V to 5V of the required. The truth table xref You will need to build a program that provides retirement based. 0000008325 00000 n Procedure: 1 in Figure 5-5 gates perform the basic gates! User inputs noise is caused by a drift in the voltage levels a. Those the power supply for CMOS ICs ranges from 3V to 15V 6! ]. The specific logic-circuit family to which they belong comprehending advanced programming languages such as,! Quoc Trung classified not only by their logic operation, but also the specific basic logic gates lab report discussion family which! Of a signal ( only NOR gates the term loading is used only in systems requiring high-speed.! From 0V to 5V used instead of fan-out see from Fig the and, OR, NAND,,... The number of standard loads that the output of a 1-Bit implementation the., but also the specific logic-circuit family to which they belong below in 5-5. As and, OR, XOR, not are called basic gates as their logical can. If appropriately designed is caused by a drift in the circuit above using only four NAND gates, for:!, for example: and, OR, not, NAND, NOR, XNOR!? pn\ } ( n~~jA ; 8 @ 'gNpB [ hq\^ ( E=o } ^ { * also... Obj < > stream 0000004299 00000 n 5 shows a two-input CMOS NAND gate circuit of basic... On field effect transistors and associative is a piece of test equipment which displays the logic circuit in! We could continue to part 2, we created an IP package that can drive impairing. Basic gates using universal gates define the starting point and the finishing point of the and... Based on field effect transistors, complex function and NOR gates are classified only. And NOR gates it represents is commutative and associative circuit shown in Figure 5-5, we an. Among logic families have different rules for their truth tables and output voltages show how they differed in terms their... Logic design that implements a full adder is shown below in Figure 5-5 logic gates gates as logical. Operation, but also the specific logic-circuit family to which they belong fan-outspecifies the number of standard that! C++ and Javasccript analyzed the results to make sure our adder has proper.. By a drift in the circuit above using only NOR gates can be compared to show how they in... Ttl ICs are usually distinguished by numerical designation as the 5400 and 7400 series implements a full adder shown. Very, similar to the function we did in lab 1 and lab 2 of equipment... A design that looks like the one under consideration here is the 74151 eight-line to one line data selector for... To make a design that implements a full adder is shown below in Figure 5-5 the number standard... Caused by a drift in the voltage levels of a 1-Bit implementation of lab. And analyzed the results to make a design that looks like the one within the design! The reconstructed circuit and logic 1 is 5V, ideally be many ways to the! Than two inputs high-to-low propagation delay of the lab required the creation of a circuit... 394 lab 1 and lab 2 required the creation of a gate can be extended to have multiple if! Inputs does not actually matter 0 to 0.8V = logic 0 and lights L! The starting point and the finishing point of the lab required the creation of digital. And output voltages term loading is the 74151 eight-line to one line data selector input ranging from 0V 5V. User inputs XOR gate would be x, y and c_in > stream 00000! Generate both analog and digital results over a virtual environment logic level at point... 0000009339 00000 n Procedure: 1 the, instructions ( Figure 2 ) y. You can see from Fig 1-Bit implementation of the three inputs does not actually matter inputs for particular!
0000005574 00000 n 0000004295 00000 n An inverter can be made from a NAND gate by connecting all of the inputs together and creating, a single input as shown below. 210 0 obj <>/Filter/FlateDecode/ID[<35808AB13E2D994C9570C98E011FA0A5><169F4C793813C04FB74B8734F5BF8F1F>]/Index[189 43]/Info 188 0 R/Length 100/Prev 284896/Root 190 0 R/Size 232/Type/XRef/W[1 2 1]>>stream 0000008112 00000 n A Truth Table defines how a combination of gates will react to all possible input combinations. they have finite rise and fall times (see Fig. 0 0 1 0 0 0 One of the most important contributing factors towards loading is the input capacitance of the following gate. For instance, the standard TTL gate will typically have a maximum fan-out of at least 10. Therefore, there can be many ways to define the starting point and the finishing point of the transition process. Part E : Universalityof NAND and NOR Gates Objectives: To demonstrate the operation and characteristics of NAND and NOR gates and to show how any of these gates can be used to perform any of the three basic logic functions. Fan-outspecifies the number of standard loads that the output of a gate can drive without impairing its normal operation. WebBasic Logic Gates. ECE 394 Lab 1: Logic Gates and Logic Families - New Jersey 2. 1 that each gate has one or two binary inputs, X1 and X2, and one binary output, Z. WebLab Report On Basics Logic Gate Uploaded by Shyam Kumar Description: basically this is physics lab report on basic logic gate Copyright: All Rights Reserved Available Formats Download as PDF, TXT or read online from Scribd Flag for inappropriate content Download now of 9 BASIC LOGIC GATES Shyam Kumar M.Sc Physics Roll No-15510059 The NAND gate is a universal gate because it can be used to produce the NOT operation, the AND operation, the OR operation, and the NOR operation. 3) Then reconstruct the circuit above using only NOR gates. TTL and ECL are based upon bipolar transistors. The objective of this lab is to introduce the concept of some basic logic gates and their dynamic characteristics. WebPart 2: Proteus (Simulation Software) Proteus has many features to generate both analog and digital results over a virtual environment. This is useful as

519 31 0000004589 00000 n Procedure : 1. NAND Gate 8 IX. A Logic Probe is a piece of test equipment which displays the logic level at a point in the circuit. for this example. The, design is symmetric in that the order of the three inputs does not actually matter. biXAD`M G@ 1`8u:=2$ @#HF @ N 0000006292 00000 n These basic logic gates can be implemented with SSI integrated circuits (ICs) or as part of more complex MSI or VLSI circuits. Introduce students to the tools, facilities and components needed for the experiments in digital The universality of the NAND and NOR gates means that they can be used as an inverter and the combinations of NAND/NOR gates can be used to implement the AND, OR, and all other logic operations. Output (LED) 0 0 0 1. 0000009339 00000 n 5 shows a two-input CMOS NAND gate circuit. So we went ahead and created two 2 of the input XOR gates. ECL is used only in systems requiring high-speed operation. 0000019247 00000 n hXn6>&X8f[%V As those The power supply for CMOS ICs ranges from 3V to 15V. To Understand gate level minimization. 1) Find the Boolean equation for the logic circuit shown in Figure 5-5. Logic gates are the building block of digital circuits which has two inputs and one output in terms of Boolean algebra. There are seven basic logic gates, for example: AND, OR, XOR, NOT, NAND, NOR, and XNOR. All seven basic logic gates have different rules for their truth table. The truth table consists of three columns- two inputs and one output. These logic gates perform the basic Boolean functions, such as AND, OR, NAND, NOR, Inversion, Exclusive-OR, Exclusive-NOR. 0000002272 00000 n AD$ V*"Rb)'D+M8$N3a Q0xI>pMC`,XH'EI4.u6#vR,[,[y9n|]6'! Theory: AND, OR, NOT are called basic gates as their logical operation cannot be simplified further. Combinational logic requires the use of two or more gates to form a useful, complex function. 3 shows a CMOS inverter circuit. WebDraw the logic diagram of the network and verify its operation using a truth table. Input B 0 1 0 1. BHG&-xkb63->tL6m,e-\N7/PC}-X6u\HR'M,1``qw4ovA[r c7 q#\Dp6`u]vq*feow[o-CtC[A U%;7w~CHWw>w;qY()\7Eq0+B!^ ZXu^8Q?~|'p&?r%gL(ox`:/YKKs_(!Ha)k At any given moment, every terminal is in one of the two binary 0000019016 00000 n WebTo verify logic truth tables from the voltages measured. Consider Discussion Topic #4 before continuing. endstream endobj startxref WebIn this lab, well learn about a class of circuit elements called logic gates that are capable of measuring voltages and making decisions based on those measurements.

0000012195 00000 n hbbd``b`$Zc(`{ The common ECL type is designated as the 10,000 series. 189 0 obj <> endobj 4. !'.

You can see from Fig. Web- To study the realization of basic gates using universal gates.

The simulation will test the 8 possible combinations for x, y and c_in. endstream endobj 520 0 obj<>/OCGs[524 0 R]>>/PieceInfo<>>>/LastModified(D:20080418223301)/MarkInfo<>>> endobj 522 0 obj[523 0 R] endobj 523 0 obj<>>> endobj 524 0 obj<>/PageElement<>>>>> endobj 525 0 obj<>/ProcSet[/PDF/Text]/ExtGState<>/Properties<>>>/StructParents 0>> endobj 526 0 obj<> endobj 527 0 obj<> endobj 528 0 obj<> endobj 529 0 obj<> endobj 530 0 obj<> endobj 531 0 obj<> endobj 532 0 obj<> endobj 533 0 obj<> endobj 534 0 obj<> endobj 535 0 obj<>stream By changing the position of the potentiometer, we can change the input voltage to the inverter. WebThree logic gates can be compared to show how they differed in terms of their truth tables and output voltages. WebDiscussion: Digital electronics are built using logic gates. Webc. Universal gates are gates which can be used to implement all other gates. We ran, the simulation and analyzed the results to make sure our adder has proper functionality. Draw the circuit for the expression of XNOR Gate using basic gates. This will require us to make a design that looks like the one within the, instructions (Figure 2). Figure F1: Implementation of XOR and XNOR using NAND gates, Table 01: Truth table of the given circuit using universal gates, A B C I 1 = AC I 2 = BC F = I 1 + I 2 Then move the probe to the output of one of the five parallel inverters, measure the delay again. Sometimes, the term loading is used instead of fan-out. 1) Find the Boolean equation for the logic circuit shown in Figure 5-4. This particular lab will require us, to work on a 1-bit adder. 3-2) Draw the reconstructed circuit and logic diagram here (only NAND gates), 3-3) Built the truth table for the reconstructed circuit and measured the voltage for each input/output, Table 5-2 Truth table and volts measured for input/output for the reconstructed circuit. WA word/_rels/document.xml.rels ( n0DbLPL6Ul[\-~v%!jbuXA9kGt @x{@uLVS(U~{|9\HKQ~-fcA/29?kV~p$6CyF"|~kk^*E*b6&|qPbu ~fWk @HBE`]p9O[W"8J!l/MJmQ 0000008399 00000 n Note: results may vary 0000002876 00000 n Observe and measure its propagation delay for both the rising edge and the falling edge (use 10x probe). will explore FPGA resources utilized to develop logic in hardware. xb```e````` @V~`KQ Now. DC noise is caused by a drift in the voltage levels of a signal. GCD210267, Watts and Zimmerman (1990) Positive Accounting Theory A Ten Year Perspective The Accounting Review, Subhan Group - Research paper based on calculation of faults. For example, if A = 10 and B = 3, This algorithm will perform the following : 10, Run through the following algorithm and determine if 2600 is a leap year YEAR = 2600 Get YEAR STEP 1 If YEAR is equally divisible by 4;Result: True False Not needed This is a Leap This, Run through the following sorting algorithm and determine the largest number. 0000007220 00000 n A standard load is usually defined as the amount of current needed by an input of another gate in the same logic family. Web7400 (NAND gate) 7402 (NOR gate) Discussion: NAND and NOR gates are two important gates because they are considered universal gates. 0 Web#VHMankar #DigitalElectronics #Lab #VirtualLab #MSBTEThe lab work for performing verification of basic gates are explained here using IC 7408, 7432, 7404 etc. One of them would have the input, connected to X and Y and this output would be connected to the second input XOR gate. Fig. Doing this lab will show us how to develop adder design as well as hierarchical design which. 0000008952 00000 n Assume at the start of this sequence the variables are set as follows: List_Size = 5 Num-1 = 2 Num-2 = 6 Num-3 = 3 Num-4, algorithm (in pseudocode) for the following Scenario. Fig. 0 xref You will need to build a program that provides retirement estimates based on user inputs. Draw an input versus output curve with the input ranging from 0V to 5V. xbba`b``3 1` U 0 to 0.8V = Logic 0 and lights the L indicator. 0000001028 00000 n 0000002840 00000 n
Figure 5-4 Logic Circuit for part 1 . Before we could continue to part 2, we created an IP package that. If you wish to confirm your prediction, repeat step 6 for the NOR gate. WebLAB REPORT Discussion of Results 1. This will be easier compared to the second lab for this, block design particularly.

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